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february 2011 doc id 17789 rev 2 1/31 31 stodd01 monolithic power management for high definition odd with true shut-down, reset, and programmable step-up voltage features 1.2 mhz dc-dc current mode pwm converter dual step-down of up to 800 ma single step-up of up to 700 ma 2 % dc output voltage tolerance for step-down 3 % dc output voltage tolerance for step-up programmable step-up output voltage by s- wire synchronous rectification power save mode at light load for step-down typical efficiency: > 90 % internal soft start with controlled inrush current reset function enable function for step-up true cut-off function for step-up low switching quiescent current: max 2.2 ma overtemperature range uses tiny capacitors and inductors available in qfn16 (4 x 4 mm.) description the stodd01 is a complete power management for blu-ray, based on high density optical storage devices. it integrates two step-down converters and one step-up. the step-down converters are optimized for powering low-voltage digital core, up to 0.8 a, in odd applications and, generally, to replace the high current linear solution when power dissipation may cause a high heating of the application environment. the step-up provides the necessary voltage to supply the blue laser in mobile applications where only 5 v is available. the output voltage is programmable by using the s-wire protocol, in the range of 6.5 v to 14 v, with a current capability of 0.7 a. the integrated low r dson for n-channel and p-channel mosfet switches contribute to obtaining high efficiency. the enable function for the step-up section, and reset function for monitoring the input voltage, make the device particularly suitable for optical storage applications. the high switching frequency (1.2 mhz typ.) allows the use of tiny surface mounted components. furthermore, a low output ripple is achieved by the current mode pwm topology and by the use of x7r or x5r low esr smd ceramic capacitors. the device includes soft-start control, thermal shutdown, and peak current limit, to prevent damage due to accidental overload. the stodd01 is packaged in qfn16 (4 x 4 mm.). qfn16l (4 x 4 mm.) table 1. device summary part number order code marking package stodd01 STODD01PQR odd01 qfn16 (4 x 4 mm.) www.st.com
contents stodd01 2/31 doc id 17789 rev 2 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 s-wire protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1 brief overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2 enable pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.3 tx pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4 reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.5 overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.6 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 typical performance characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.2 programming the output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.3 inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.4 input and output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.5 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10 recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
stodd01 block diagram doc id 17789 rev 2 3/31 1 block diagram figure 1. stodd01 block diagram step-down 800ma step-down 800ma reset step-up 700ma gnd gnd sw1 out1 fb1 sw2 fb2 sw3 fb3 v in_a en tx v in_p reset gnd gnd s-wire ch1 ch2 ch3 step-down 800ma step-down 800ma reset step-up 700ma gnd gnd sw1 out1 fb1 sw2 fb2 sw3 fb3 v in_a en tx v in_p reset gnd gnd s-wire ch1 ch2 ch3
absolute maximum ratings stodd01 4/31 doc id 17789 rev 2 2 absolute maximum ratings note: absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. table 2. absolute maximum ratings symbol parameter value unit v in_a analog input voltage - 0.3 to 7 v v in_p power input voltage - 0.3 to 7 v en enable voltage - 0.3 to 7 v sw1 switch pin for ch1 - 0.3 to 16 v sw2,sw3 switch pin for ch2 and ch3 - 0.3 to 7 v out1 output voltage for ch1 - 0.3 to 16 v fb1 feedback pin for ch1 - 0.3 to 2.5 v fb2 feedback pin for ch2 - 0.3 to 5 v fb3 feedback pin for ch3 - 0.3 to 2.5 v reset reset pin - 0.3 to v in + 0.3 v tx s-wire pin - 0.3 to 7 v t j maximum junction temperature 150 c t stg storage temperature range - 65 to + 150 c t jop operating junction temperature range - 25 to + 125 c table 3. thermal data symbol parameter value unit r thjc thermal resistance junction-case 2.5 c/w r thja thermal resistance j unction-ambient 46 c/w table 4. esd symbol parameter value unit hbm human body model 2 kv mm machine model 200 v
stodd01 pin configuration doc id 17789 rev 2 5/31 3 pin configuration figure 2. pin connection (top through view) table 5. pin description pin n symbol name and function 1 gnd_p power ground pin (ch1) 2 fb1 step-up feedback pin (ch1) 3v in_a power supply for internal analog circuits 4 fb2 step-down feedback pin (ch2) 5 gnd_p power ground pin (ch2) 6 sw2 step-down switching pin (ch2) 7v in_p power input voltage pin 8 sw3 step-down switching pin (ch3) 9 gnd_p power ground pin (ch3) 10 fb3 step-down feedback pin (ch3) 11 gnd_a analog ground pin 12 out1 step-up output voltage 13 tx s-wire pin. if connected to gnd, v fb1 =0.8v (1) 14 sw1 step-up switching pin (ch1) 15 en enable pin. connecting the pin to a vo ltage higher than 1.2 v the step-up is on.connecting the pin to a voltage lowe r than 0.4 v the step-up is off, resulting in no curre nt flow to the load 16 reset reset pin. it is an open drain output exposed pad ground and thermal dissipation pad 1. if this function is not used, the tx pin must be connected to gnd
typical application stodd01 6/31 doc id 17789 rev 2 4 typical application note: if the s-wire function is not used, the tx pin must be connected to gnd. figure 3. application circuit out1 fb1 sw2 fb2 sw3 fb3 gnd r1 r2 r3 r4 l3 l2 c5 c4 c6 v out2 v out3 v in_a v in_p reset tx en gnd sw1 l1 r5 en tx reset v out1 v in c1 c3 c2 stodd01 gnd gnd out1 fb1 sw2 fb2 sw3 fb3 gnd r1 r2 r3 r4 l3 l2 c5 c4 c6 v out2 v out3 v in_a v in_p reset tx en gnd sw1 l1 r5 en tx reset v out1 v in c1 c3 c2 stodd01 gnd gnd table 6. list of external components (1) component manufacturer p art number value size c1, c2, c3 murata grm21br61a106ke19l 10 f 0805 c4, c5, c6 murata grm32er61c226ke20l 22 f 1210 l1 coilcraft lps6225-472mlb 4.7 h 6 x 6 x 2.5 l2, l3 coilcraft lps4018-332mlb 3.3 h 4.1 x 4.1 x 1.8 r1 33 k (v out1 = 8.8 v) (2) 0603 r2 3.3 k 0603 r3 27 k (v out3 = 1.2 v) (3) 0603 r4 47 k 0603 r5 100 k (4) 0603 1. the components listed above refer to typica l applications. operation of the stodd01 is not limited to the choice of these external components. 2. r1 and r2 are calculated acco rding to the following formula: r1 = r2 x (v out1 /v fb1 - 1). it is recommended to use resistors with values in the range of 1 k to 50 k . 3. r3 and r4 are calculated acco rding to the following formula: r3 = r4 x (v out3 /v fb3 - 1). it is recommended to use resistors with values in the range of 1 k to 50 k . 4. it is recommended to use resistors with values in the range of 100k to 1m .
stodd01 electrical characteristics doc id 17789 rev 2 7/31 5 electrical characteristics v in_p = v in_a = v en = 5 v, v out1 = 9 v, v out2 = 3.3 v, v out3 = 1.2 v, c 1,2,3 = 10 f, c 4,5,6 = 22 f, l1 = 4.7 h, l2 = l3 = 3.3 h, t j = - 25 to 125 c (unless otherwise specified; typical valu es are referred to t j = 25 c). table 7. electrical characteristics symbol parameter test cond itions min. typ. max. unit v in input voltage range 4 6 v i supply supply current v en > 1.2 v, no switching 1.6 2.2 ma v en < 0.4 v, no switching 1.2 2.0 ma step-up section v out output voltage range 6.5 14 v v fb1 prog. feedback voltage range i out1 = 50 ma (prog. by s-wire see figure 9 and ta b l e 9 ) 0.776 0.8 0.824 v feedback voltage accuracy -3 3 % i fb1 feedback current v fb1 = 0 v, v en = 2 v 600 na i out1_off (leak) output leakage current v en = 0 v, t j = -25 to 80 c 20 a v out1 ovp overvoltage protection (1) v fb1 = 0 v 14.8 15.3 15.8 v r dson_n internal n-channel r dson i sw1 =400 ma 300 m r dson_p internal p-channel r dson i sw1 =400 ma 300 i sw1 (leak) internal leakage current v sw1 = 4 v, v fb1 = 2 v, v en = 0 v 2 a i sw1 (lim) sw current limitation v out1 = 9.2 v 2.6 a pwm f s oscillator frequency to be measured on t sw1 pin 0.75 1.2 1.5 mhz d max max duty cycle on sw1 pin, v fb1 = 0.7 v 70 90 % efficiency i out1 =50 ma, v out1 =7 v 80 % i out1 =700 ma, v out1 =7 v 90 % i out1 =100 ma, v out1 =9 v 75 % i out1 =700 ma, v out1 =9 v 90 % v en_h enable threshold high v in =4 to 6 v, i out1 = 50 ma 1.2 v v en_l enable threshold low v in = 4 to 6 v, i out1 = 50 ma 0.4 i en enable pin current v en = v in = 5 v 2 a v out1 / v in line transient response (2) v in from 4 to 6 v, i out1 = 500 ma, t r = t f => 30 s, t j =25 c -5 5 % v out v out1 / i out load transient response (2) v in = 5 v, i out1 from 100 ma to 500 ma, t r = t f => 5s, t j =25 c -5 5 % v out v out1 / v in startup transient (2) v in from 0 to 5 v, i out1 = 500 ma -10 10 % v out
electrical characteristics stodd01 8/31 doc id 17789 rev 2 t start startup time v en from 0 to 5 v, i out1 =100 ma 500 s inrush current v out =9.25 v, i out =100 ma 1.3 a step-down section fb 2 feedback voltage 3.23 3.3 3.37 v i fb2 fb2 pin bias current v fb2 = 3.5 v 15 20 a fb 3 feedback voltage 0.784 0.8 0.816 mv i fb3 fb3 pin bias current v fb3 = 1 v 600 na i out2,3 output current (3) v in = 4 to 6 v 700 800 ma i out_min minimum output current 0 ma v out2,3 reference load regulation 10 ma < i out2,3 < 0.8 a 5.5 15 mv pwm f s pwm switching frequency i out2,3 = 0.3 a 1.2 mhz %v out2 / v in line regulation 4 v < v in < 6 v 0.032 % v out /v in %v out3 / v in line regulation 4 v < v in < 6 v 0.15 % v out /v in d max maximum duty cycle v fb2 = 3.0 v, v fb3 = 0.7 v 85 94 % i swl switching current limitation 1.5 a i lkp2,3 pmos leakage current v fb2 = 3.5 v, v fb3 = 0.9 v, v sw2,3 = gnd, t j =- 25 to 80 c 0.1 a i lkn2,3 nmos leakage current v fb2 = 3.5 v, v fb3 = 0.9 v, v sw2,3 = 5 v, t j =- 25 to 80 c 0.1 a r dson - n nmos switch on resistance i sw = 250 ma 0.2 0.4 w r dson - p pmos switch on resistance i sw = 250 ma 0.3 0.5 w v out2,3 / i ou t2,3 load transient response (2) 100 ma < i out2,3 < 500 ma, t r = t f => 100 ns, t j = 25 c -5 +5 % v out efficiency v out3 = 1.2 v i out3 = 100 ma 65 % i out3 = 800 ma 80 efficiency v out2 = 3.3 v i out2 = 100 ma 75 % i out2 = 800 ma 90 reset section t del delay time t j = 25 c 100 ms v r_th reset threshold v in rising (see figure 12 and figure 29 ) (measured on input voltage pin) 4.3 4.4 v v r_tl v in falling (see figure 12 and figure 29 ) (measured on input voltage pin) 4.1 4.2 table 7. electrical characteristics (continued) symbol parameter test cond itions min. typ. max. unit
stodd01 electrical characteristics doc id 17789 rev 2 9/31 v rl reset output voltage low v in =4 v, i sink =6 ma open drain output 0.4 v i rh reset leakage current v in =5 v, v res =5 v, t j =-25 to 80 c 5 200 na thermal section t shdn thermal shutdown (2) 130 150 c t hys thermal shutdown hysteresis (2) 15 c 1. if v out1 > ovp voltage the device stops to switch. 2. guaranteed by design, but not tested in production. 3. v out = 90 % of nominal value table 7. electrical characteristics (continued) symbol parameter test cond itions min. typ. max. unit
s-wire protocol stodd01 10/31 doc id 17789 rev 2 6 s-wire protocol note: these are recommended values for proper operation of the s-wire interface. the s-wire input pin is able to detect pulses also outside these ranges. consequently, care must be taken to avoid noise injected into the s-wire pin. table 8. timing parameter symbol min. typ. max. unit s-wire signal start (see figure 5 , 6 , 7 , 8 )t sw_start 300 500 s s-wire signal stop (see figure 5 , 6 , 7 , 8 )t sw_stop 300 500 s s-wire signal off (see figure 5 , 6 , 7 , 8 )t sw_off 270 s s-wire high (see figure 5 , 6 , 7 , 8 )t sw_h 25 50 s s-wire low (see figure 5 , 6 , 7 , 8 )t sw_l 25 50 s s-wire rising time (see figure 4 )t sw_r 200 ns s-wire falling time (see figure 4 )t sw_f 200 ns fb voltage delay t sw_delay 20 s s-wire threshold high (see figure 4 )v sw_th 1.6 v in v s-wire threshold low (see figure 4 )v sw_tl 00.4v figure 4. s-wire pulse thresholds t sw_r t sw_f 10% 90% v sw_tl v sw_th am07818v1 t sw_r t sw_f 10% 90% v sw_tl v sw_th am07818v1
stodd01 s-wire protocol doc id 17789 rev 2 11/31 figure 5. s-wire protocol timing diagrams (case a) gnd gnd gnd gnd gnd en s-wire t sw_h t sw_l v in 5 v 5 v t sw_start t sw_stop 2 3 4 1 t sw_start t sw_delay v fb1 v out1 0.8 v 9 v 9.675 v t sw_start 9.675 v set by resistor divider 0.86 v 0.86 v en s-wire t t v in 2 3 4 1 v fb1 v out1 - gnd gnd gnd gnd gnd en s-wire t sw_h t sw_l v in 5 v 5 v t sw_start t sw_stop 2 3 4 1 t sw_start t sw_delay v fb1 v out1 0.8 v 9 v 9.675 v t sw_start 9.675 v set by resistor divider 0.86 v 0.86 v en s-wire t t v in 2 3 4 1 v fb1 v out1 - figure 6. s-wire protocol timing diagrams (case b) gnd gnd gnd gnd gnd t sw_start en s-wire v fb1 v out1 0.86v 9.675v t sw_h t sw_l 0.86v 9.675v v in 5v 5v t sw_start t sw_stop 2 3 4 1 gnd gnd gnd gnd gnd t sw_start en s-wire v fb1 v out1 0.86v 9.675v t sw_h t sw_l 0.86v 9.675v v in 5v 5v t sw_start t sw_stop 2 3 4 1 gnd gnd gnd gnd gnd t sw_start en s-wire v fb1 v out1 0.86v 9.675v t sw_h t sw_l 0.86v 9.675v v in 5v 5v t sw_start t sw_stop 2 2 3 3 4 4 1 1
s-wire protocol stodd01 12/31 doc id 17789 rev 2 figure 7. s-wire protocol timing diagrams (case c) gnd gnd gnd gnd gnd en s-wire t sw_h t sw_l v in 5v 5v t sw_start 2 3 4 1 t sw_start t sw_delay v fb1 v out1 0.8v 9v 9.675v 9.338v set by resistor divider 0.86v 0.83v 2 1 t sw_stop t sw_stop 0.8v 9v t sw_off gnd gnd gnd gnd gnd en s-wire t sw_h t sw_l v in 5v 5v t sw_start 2 2 3 3 4 4 1 1 t sw_start t sw_delay v fb1 v out1 0.8v 9v 9.675v 9.338v set by resistor divider 0.86v 0.83v 2 2 1 1 t sw_stop t sw_stop 0.8v 9v t sw_off figure 8. s-wire protocol timing diagrams (case d) 9.338v 0.83v gnd gnd gnd en s-wire t sw_h t sw_l v in 5v 5v t sw_start 2 3 4 1 t sw_start t sw_delay v fb1 v out1 0.8v 9v 9.675v set by resistor divider 0.86v gnd gnd 2 1 t sw_stop t sw_stop 0.8v 0.9v t sw_off t sw_start 9.338v 0.83v gnd gnd gnd en s-wire t sw_h t sw_l v in 5v 5v t sw_start 2 2 3 3 4 4 1 1 t sw_start t sw_delay v fb1 v out1 0.8v 9v 9.675v set by resistor divider 0.86v gnd gnd 2 2 1 1 t sw_stop t sw_stop 0.8v 0.9v t sw_off t sw_start
stodd01 s-wire protocol doc id 17789 rev 2 13/31 table 9. feedback one voltage level s-wire pulses v fb1 (v) s-wire pulses v fb1 (v) s-wire pulses v fb1 (v) 0 (default value) 0.800 11 0.965 22 1.130 1 0.815 12 0.980 23 1.145 2 0.830 13 0.995 24 1.160 3 0.845 14 1.010 25 1.175 4 0.860 15 1.025 26 1.190 5 0.875 16 1.040 27 1.205 6 0.890 17 1.055 28 1.220 7 0.905 18 1.070 29 1.235 8 0.920 19 1.085 30 1.250 9 0.935 20 1.100 10 0.950 21 1.115 figure 9. single wire programming 1 s-wire v fb1 =0.815v s-wire v fb1 =0.8v (default value) 12 s-wire v fb1 =0.830v 1 2 3 s-wire v fb1 =0.845v 1234 s-wire v fb1 =0.860v 12345 s-wire v fb1 =0.875v s-wire 26 28 27 v fb1 =1.22v 12345 s-wire 26 28 29 27 v fb1 =1.235v 12345 s-wire 12345 26 28 29 30 27 v fb1 =1.25v s-wire v fb1 =0.8v 1 s-wire v fb1 =0.815v s-wire v fb1 =0.8v (default value) 12 s-wire v fb1 =0.830v 1 2 3 s-wire v fb1 =0.845v 1234 s-wire v fb1 =0.860v 12345 s-wire v fb1 =0.875v s-wire 26 28 27 v fb1 =1.22v 12345 s-wire 26 28 29 27 v fb1 =1.235v 12345 s-wire 12345 26 28 29 30 27 v fb1 =1.25v s-wire v fb1 =0.8v
detailed description stodd01 14/31 doc id 17789 rev 2 7 detailed description 7.1 brief overview the stodd01 is a complete high efficiency switching power management. inside it has a step-up converter with a current capability up to 0.7 a and two step-down converters with a current capability up to 0.8 a. the controller uses an average current mode technique in order to obtain good stability in all application conditions. the step-up converter, in order to guarantee the lowest switching ripple, operates in pwm (pulse width modulation) in all load conditions. both step-down converters, in order to maintain good efficiency, operate in power-save mode at light load. when the load increases, they automatically switch to pwm (pulse width modulation) mode and the output voltage ripple is minimized. the stodd01 is self protected against overtemperature and accidental short circuit in the step down channel. the soft-start function guarantees proper operation during startup. 7.2 enable pin the step-up section operates when the en pin is set high. if the en pin is set low the step- up turns off. in this condition the supply current is lower than 2 ma in the whole temperature range, and it represents the consumption of the step-down section. when the en pin is low, thanks to at the true cut-off function, implemented using two p- channel mosfets in a back-to-back configuration, as shown in figure 10 , the output current is stopped. in order to control and reduce the in-rush current, the true cut-off p- channel (p o ) manages the current during startup. figure 10. true cut-off block sw1 pgnd ps out1 po ns sw1 pgnd ps out1 po ns
stodd01 detailed description doc id 17789 rev 2 15/31 figure 32 shows the in-rush current at enable transient. initially, the c 4 capacitor is completely discharged and the current limitation is due only to the equivalent series resistor of the inductor, the power mosfet parasitic diode, and the cut-off mosfets? r dson . as soon as the output voltage reaches the input voltage level, the device begins to switch and the current is limited cycle by cycle. the en pin does not have an internal pull-up, which means that the enable pin cannot be left floating. if the enable function is not used, the en pin must be connected to v in . 7.3 tx pin the device implements an s-wire bus communic ation, which uses one control signal coming from the microprocessor to program the step-up stodd01 output voltage (see figure 11 ). s-wire protocol allows the feedback voltage of the step-up section to be changed from 0.8 to 1.25 v, with steps of 15 mv (see ta bl e 9 ). this feature allows complete and easy control of the laser diode power during read and write operation. if this function is not used, the tx pin must be connected to gnd. 7.4 reset function this flag shows that input voltage is in the correct range. a comparator senses the input voltage. when it is higher than v r_th , the reset pin goes to high impedance, with a delay of 100 ms (typ.). if it is below v r_tl , the reset pin goes to low impedance (see figure 12 ). figure 11. s-wire connection reset tx en gnd en tx reset stodd01 gnd gnd p gnd
detailed description stodd01 16/31 doc id 17789 rev 2 the use of the reset function requires an external pull-up resistor which must be connected between the reset pin and v in or any v out voltage lower than 5 v. a pull-up resistor for reset in the range of 100 k to 1 m is recommended. if the reset function is not used, the reset pin may remain floating on the board. 7.5 overtemperature protection an internal temperature sensor continuously monitors the ic junction temperature. if the ic temperature exceeds 150 c (typ.) the device stops operating. as soon as the temperature falls below 135 c (typ.) normal operation is restored. 7.6 overvoltage protection the device provides overvoltage protection for monitoring the step-up output voltage. if the sensed voltage on ch1 output exceeds 15.3 v (typ.) the step-up channel stops switching. as soon as the output capacitor is discharged and the sensed voltage is below 14.8 v, it re-starts to switch (see figure 13 ). figure 12. reset function v r_tl v r_th v in reset t del v r_tl v r_th v in reset t del figure 13. ovp function 15.3v 14.8v output voltage no switching switching switching ovp signal
stodd01 typical performance characteristics doc id 17789 rev 2 17/31 8 typical performance characteristics c 1,2,3 = 10 f, c 4,5,6 = 22 f, l1 = 4.7 h, l2 = l3 = 3.3 h. figure 14. supply current vs. temperature figure 15. feedback voltage vs. temperature figure 16. feedback voltage vs. temperature figure 17. feedback voltage vs. temperature figure 18. ovp vs. temperature figure 19. true shutdown voltage vs. temperature 0 0.5 1 1.5 2 2.5 -40 -20 0 20 40 60 80 100 120 140 temperature [c] supply current [ma] v in_a =v in_p =5v, v en <=0.4v, no switching 0.77 0.78 0.79 0.8 0.81 0.82 0.83 -40 -20 0 20 40 60 80 100 120 140 temperature [c] v fb1 [v] v in_a = v in_p = 5v, v en = 5v, i out1 = 50ma 3.27 3.28 3.29 3.3 3.31 3.32 -40 -20 0 20 40 60 80 100 120 140 temperature [c] v fb2 [v] v in_a = v in_p = 5v, v en = 5v, i out2 = no load 0.77 0.78 0.79 0.8 0.81 0.82 0.83 -40 -20 0 20 40 60 80 100 120 140 temperature [c] v fb3 [v] v in_a = v in_p = 5v, v en = 5v, i out3 = no load 14.5 14.7 14.9 15.1 15.3 15.5 -40 -20 0 20 40 60 80 100 120 140 temperature [c] ovp [v] v in_a = v in_p = 5v, v en = 5v, v fb1 = gnd -0.002 0 0.002 0.004 0.006 0.008 0.01 -40-20 0 20406080100 temperature [c] v out1_off [v] v in_a = v in_p = 5v, v en = 0v, i out1 = no load
typical performance characteristics stodd01 18/31 doc id 17789 rev 2 figure 20. output leakage current vs. temperature figure 21. sw current limitation vs. temperature figure 22. sw current limitation vs. temperature figure 23. sw current limitation vs. temperature figure 24. oscillator frequency vs. temperature figure 25. enable vs. temperature -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 -40 -20 0 20 40 60 80 100 temperature [c] i leak_vout [a] v in_a = v in_p = 5v, v en = 0v, v out1 = gnd 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 -40-20 0 20406080100120140 temperature [c] i swl1 [a] v in_a = v in_p = 5v, v en = 5v, v out1 = 9.25v (measured @v out1 = v out1_nom - 10%) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 -40 -20 0 20 40 60 80 100 120 140 temperature [c] i swl2 [a] v in_a = v in_p = 6v, v en = 6v, v out2 = 3.25v (measured @v out2 = v out2_nom - 10%) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 -40 -20 0 20 40 60 80 100 120 140 temperature [c] i swl3 [a] v in_a = v in_p = 6v, v en = 6v, v out3 = 1.2v (measured @v out3 = v out3_nom - 10%) 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 -40 -20 0 20 40 60 80 100 120 140 temperature [c] frequency [mhz] v in_a = v in_p = 5v, v en = 1.2v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -40 -20 0 20 40 60 80 100 120 140 temperature [c] enable threshold (v) ven_h ven_th v in_a = v in_p = 6v, v out1 = 7v, i out1 = 50ma
stodd01 typical performance characteristics doc id 17789 rev 2 19/31 figure 26. enable vs. temperature figure 27. efficiency step-up vs. output current figure 28. efficiency step-down vs. output current figure 29. reset threshold vs. temperature all efficiencies are relative to one channel, the other channel is at no-load. figure 30. startup transient figure 31. enable transient 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -40 -20 0 20 40 60 80 100 120 140 temperature [c] enable threshold (v) ven_h ven_th v in_a = v in_p = 4v, v out1 = 7v, i out1 = 50ma 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 iout [ma] efficiency [%] vout=7v vout=9.2v v in_a = v in_p = 5v, v en = 1.2v 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 iout [ma] efficiency [%] vout=3.3v vout=1.2v v in_a = v in_p = 5v, v en = 5v 4.12 4.17 4.22 4.27 4.32 4.37 4.42 -40 -20 0 20 40 60 80 100 120 140 temperature [c] reset threshold (v) vr_th vr_tl v in_p = v in_a = v en v out1 v out2 v out3 v in_a = v in_p = v en from 0 to 5v, v out1 = 9.2v, i out1 = 500ma, t rise = 100s v en v out1 v out2 v out3 v in_a = v in_p = 5v, v en from 0 to 5v, v out1 = 9.2v, i out1 = 100ma
typical performance characteristics stodd01 20/31 doc id 17789 rev 2 figure 32. inrush current figure 33. s-wire protocol v en v in i in v in_a = v in_p = 5v, v en from 0 to 5v, v out1 = 9.2v, i out1 = 100ma v out1 5 ? pulses ? sequence 30 ? pulses ? sequence default ? value v v en v in_a = v in_p = 5v, v en from 0 to 5v
stodd01 application information doc id 17789 rev 2 21/31 9 application information 9.1 introduction the following is some technical information for estimating the typical external components characteristics using standard literature equations. nevertheless, it is strongly recommended to validate t he external components suit ability to the application requirements, thoroughly testing any solution at bench level on a real evaluation circuit. 9.2 programming the output voltage the output voltage for the step-up (ch1) can be adjusted from 6.5 v up to 14 v by connecting a resistor divider between the v out1 and the gnd, the middle point of the divider must be connected to the fb1 pin, as shown in figure 3 . the resistor divider should be chosen in accordance with the following equation: equation 1 it is recommended to use a resistor with a value in the range of 1 k to 50 k . lower values can also be suitable, but in crease curren t consumption. for ch2 the device integrates the resistor divider needed to set the correct output voltage. this allows 2 external components to be saved. the fb2 pin must be connected directly to v out2 . the output voltage for ch3 can be adjusted from 0.8 v up to 85 % of the input voltage value by connecting a resistor divider between v out3 and gnd, the middle point of the divider must be connected to fb3 pin, as shown in figure 3 . the resistor divider must be chosen according to the following equation: equation 2 using a resistor with a value in the range of 1 k to 50 k is recommended . lower values are also suitable, but increase current consumption. 9.3 inductor selection the inductor is the key passive component for switching converters. the inductor selection must take the boundary conditions in which th e converter works into consideration, the maximum input voltage for the buck and the minimum input voltage for the boost. ? ? ? ? ? ? + = 2 r 1 r 1 v v 1 fb 1 out ? ? ? ? ? ? + = 4 r 3 r 1 v v 3 fb 3 out
application information stodd01 22/31 doc id 17789 rev 2 the critical inductance values can then be obtained according to the following formulas: for the step-down equation 3 and for the step-up equation 4 where: f sw : switching frequency i l = the peak-to-peak inductor ripple current. as a rule of thumb, the peak-to-peak ripple can be set at 20 % - 40 % of the output current for the step-down and can be set at 20 % - 40 % of the input current for the step-up. the peak current of the inductor can be calculated as: equation 5 equation 6 in addition to the inductance value, in order to avoid saturation, the maximum saturation current of the inductor must be higher than that of the i peak . 9.4 input and output capacitor selection it is recommended to use ceramic capacitors with x5r or x7r dielectric and low esr as input and output capacitors, in order to filter any disturbance present in the input line and to obtain stable operation. the output capacitor is very important for satisfying the output voltage ripple requirement. the output voltage ripple (v out_ripple ), in continuous mode, for the step-down channel, can be calculated: l sw max _ in out max _ in out min i f v ) v v ( v l ? = l sw out min _ in out min _ in min i f v ) v v ( v l ? = l f v 2 ) v v ( v ) 8 . 0 / i ( i sw max _ in out max _ in out out down _ step peak ? + = ? l f v 2 ) v v ( v v i v i sw out min _ in out min _ in min _ in out out up _ step peak ? + = ?
stodd01 application information doc id 17789 rev 2 23/31 equation 7 where i l is the ripple current and f sw is the switching frequency. the output voltage ripple (v out_ripple ), in continuous mode, for the step-up channel, is: equation 8 where f sw is the switching frequency. the use of ceramic capacitors with voltage ratings in the range higher than 1.5 times the maximum input or output voltage is recommended. 9.5 layout considerations due to the high switching frequency and peak current, the layout is an important design step for all switching power supplies. important para meters (efficiency, ou tput voltage ripple, switching noise immunity, etc.) can be affected if the pcb layout is not designed with close attention to the following dc-dc g eneral layout rules, such as: short, wide traces must be implemented for mains current and for power ground paths. the input capacitor must be placed as close as possible to the ic pins as well as the inductor and output capacitor. the feedback pin (fb) connection to the exte rnal resistor divider is a high impedance node, so interference can be minimized by placing the routing of the feedback node as far as possible from the high current paths. to reduce pick up noise the resistor divider must be placed very close to the device. a common ground node minimizes ground noise. the exposed pad of the package must be connected to the common ground node. moreover, the exposed pad ground connection must be properly designed in order to facilitate the heat dissipation from the exposed pad to the ground layer using pcb vias, as shown in the recommended pcb layout of figure 34 , 35 , and 36 . ? ? ? ? ? ? + = sw out l ripple _ out f c 8 1 esr i v ( ) ? ? ? ? ? ? ? + = sw out out in out out ripple _ out f c v v v esr i v
recommended pcb layout stodd01 24/31 doc id 17789 rev 2 10 recommended pcb layout figure 34. component placement figure 35. top layer routing
stodd01 recommended pcb layout doc id 17789 rev 2 25/31 figure 36. bottom layer routing
package mechanical data stodd01 26/31 doc id 17789 rev 2 11 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions, and product status, are available at www.st.com . ecopack is an st trademark. table 10. qfn16 (4 x 4 mm.) mechanical data dim. mm. min. typ. max. a 0.80 0.90 1.00 a1 0.00 0.02 0.05 a3 0.20 b 0.25 0.30 0.35 d 3.90 4.00 4.10 d2 2.50 2.80 e 3.90 4.00 4.10 e2 2.50 2.80 e0.65 l 0.30 0.40 0.50
stodd01 package mechanical data doc id 17789 rev 2 27/31 figure 37. qfn16 (4 x 4 mm.) drawing 7571203_a
package mechanical data stodd01 28/31 doc id 17789 rev 2 dim. mm. inch. min. typ. max. min. typ. max. a 33 0 12. 99 2 c 12. 8 1 3 .2 0.504 0.51 9 d 20.2 0.7 9 5 n 99 101 3 . 898 3 . 9 76 t 14.4 0.567 ao 4. 3 5 0.171 bo 4. 3 5 0.171 ko 1.1 0.04 3 po 4 0.157 p 8 0. 3 15 tape & reel qfnxx/dfnxx (4x4) mechanical data
stodd01 package mechanical data doc id 17789 rev 2 29/31 figure 38. qfn16 (4 x 4) footprint recommended data (dimension in mm.)
revision history stodd01 30/31 doc id 17789 rev 2 12 revision history table 11. document revision history date revision changes 03-aug-2010 1 first release. 28-feb-2011 2 updated qfn16 mechanical data table 10 on page 26 , figure 37 on page 27 .
stodd01 doc id 17789 rev 2 31/31 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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